CVE-2018-5407

Published Nov 15, 2018

Last updated 4 days ago

Overview

Description
Simultaneous Multi-threading (SMT) in processors can enable local users to exploit software vulnerable to timing attacks via a side-channel timing attack on 'port contention'.
Source
cret@cert.org
NVD status
Modified

Risk scores

CVSS 3.1

Type
Primary
Base score
4.7
Impact score
3.6
Exploitability score
1
Vector string
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:H/I:N/A:N
Severity
MEDIUM

CVSS 2.0

Type
Primary
Base score
1.9
Impact score
2.9
Exploitability score
3.4
Vector string
AV:L/AC:M/Au:N/C:P/I:N/A:N

Weaknesses

cret@cert.org
CWE-200
nvd@nist.gov
CWE-203

Social media

Hype score
Not currently trending

Configurations

References